Commit 4bb90087 authored by Andy Polyakov's avatar Andy Polyakov
Browse files

x86[_64]cpuid.pl: harmonize usage of reserved bits #20 and #30.

parent 67150340

crypto/rc4/asm/rc4-x86_64.pl

+5 −7
Original line number Diff line number Diff line
@@ -159,8 +159,8 @@ $code.=<<___; 
	movl	($dat,$XX[0],4),$TX[0]#d

	test	\$-16,$len

	jz	.Lloop1

	bt	\$30,%r8d	# Intel CPU Family 6

	jc	.L16x

	bt	\$30,%r8d	# Intel CPU?

	jc	.Lintel

	and	\$7,$TX[1]

	lea	1($XX[0]),$XX[1]

	jz	.Loop8
@@ -217,7 +217,7 @@ $code.=<<___; 
	jmp	.Lexit



.align	16

.L16x:

.Lintel:

	test	\$-32,$len

	jz	.Lloop1

	and	\$15,$TX[1]
@@ -438,10 +438,8 @@ RC4_set_key: 
	xor	%r11,%r11



	mov	OPENSSL_ia32cap_P(%rip),$idx#d

	bt	\$20,$idx#d	# Intel CPU

	jnc	.Lw1stloop

	bt	\$30,$idx#d	# Intel CPU Family 6

	jnc	.Lc1stloop

	bt	\$20,$idx#d	# RC4_CHAR?

	jc	.Lc1stloop

	jmp	.Lw1stloop



.align	16

crypto/x86_64cpuid.pl

+4 −3
Original line number Diff line number Diff line
@@ -124,13 +124,14 @@ OPENSSL_ia32_cpuid: 
.Lnocacheinfo:

	mov	\$1,%eax

	cpuid

	and	\$0xbfefffff,%edx	# force reserved bits to 0

	cmp	\$0,%r9d

	jne	.Lnotintel

	or	\$0x00100000,%edx	# use reserved 20th bit to engage RC4_CHAR

	or	\$0x40000000,%edx	# set reserved bit#30 on Intel CPUs

	and	\$15,%ah

	cmp	\$15,%ah		# examine Family ID

	je	.Lnotintel

	or	\$0x40000000,%edx	# use reserved bit to skip unrolled loop

	jne	.Lnotintel

	or	\$0x00100000,%edx	# set reserved bit#20 to engage RC4_CHAR

.Lnotintel:

	bt	\$28,%edx		# test hyper-threading bit

	jnc	.Lgeneric

crypto/x86cpuid.pl

+6 −4
Original line number Diff line number Diff line
@@ -92,13 +92,15 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } 
&set_label("nocacheinfo");

	&mov	("eax",1);

	&cpuid	();

	&and	("edx",~(1<<20|1<<30));	# force reserved bits to 0

	&cmp	("ebp",0);

	&jne	(&label("notP4"));

	&jne	(&label("notintel"));

	&or	("edx",1<<30);		# set reserved bit#30 on Intel CPUs

	&and	(&HB("eax"),15);	# familiy ID

	&cmp	(&HB("eax"),15);	# P4?

	&jne	(&label("notP4"));

	&or	("edx",1<<20);		# use reserved bit to engage RC4_CHAR

&set_label("notP4");

	&jne	(&label("notintel"));

	&or	("edx",1<<20);		# set reserved bit#20 to engage RC4_CHAR

&set_label("notintel");

	&bt	("edx",28);		# test hyper-threading bit

	&jnc	(&label("generic"));

	&and	("edx",0xefffffff);

doc/crypto/OPENSSL_ia32cap.pod

+2 −3
Original line number Diff line number Diff line
@@ -37,14 +37,13 @@ moment of this writing following bits are significant: 
=item bit #28 denoting Hyperthreading, which is used to distiguish

      cores with shared cache;



=item bit #30, reserved by Intel, is used to choose among RC4 code

      paths;

=item bit #30, reserved by Intel, denotes specifically Intel CPUs;



=item bit #33 denoting availability of PCLMULQDQ instruction;



=item bit #41 denoting SSSE3, Supplemental SSE3, support;



=item bit #43 denoting AMD XOP support (forced to zero on Intel);

=item bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);



=item bit #57 denoting AES-NI instruction set extension;