Loading ttcn/SremSsem/LibItsSremSsem_TestSystem.ttcn +1 −0 Original line number Original line Diff line number Diff line Loading @@ -64,6 +64,7 @@ module LibItsSremSsem_TestSystem { */ */ type component ItsSremSsemSystem { type component ItsSremSsemSystem { port AdapterControlPort acPort; port UpperTesterPort utPort; port UpperTesterPort utPort; port SremSsemPort sremSsemPort; port SremSsemPort sremSsemPort; Loading Loading
ttcn/SremSsem/LibItsSremSsem_TestSystem.ttcn +1 −0 Original line number Original line Diff line number Diff line Loading @@ -64,6 +64,7 @@ module LibItsSremSsem_TestSystem { */ */ type component ItsSremSsemSystem { type component ItsSremSsemSystem { port AdapterControlPort acPort; port UpperTesterPort utPort; port UpperTesterPort utPort; port SremSsemPort sremSsemPort; port SremSsemPort sremSsemPort; Loading