Commit dd302fd0 authored by zeiss's avatar zeiss
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parent c4b31696
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+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@
 ** @verdict  pass reject
 *****************************************************************/

module Syn_0803_ModuleControlPart_001 {
module NegSyn_0803_ModuleControlPart_001 {

control {
	
+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@
 ** @verdict  pass reject
 *****************************************************************/

module Syn_0803_ModuleControlPart_002 {
module NegSyn_0803_ModuleControlPart_002 {

control {
	var integer count := 0;	
+3 −3
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@
 ** @verdict  pass accept, noexecution
 *****************************************************************/

module Syn_0803_ModuleControlPart_001 {
module Syn_0803_ModuleControlPart_002 {

type component GeneralComp {}

@@ -14,7 +14,7 @@ type record MyRecordType {
	charstring field2
}

testcase Syn_0803_ModuleControlPart_001() runs on GeneralComp {
testcase Syn_0803_ModuleControlPart_002() runs on GeneralComp {
	setverdict(pass);
}

@@ -24,7 +24,7 @@ control {
	timer t_mytimer;
	t_mytimer.start;
	if (v_i == 1) {
		execute(Syn_0803_ModuleControlPart_001());
		execute(Syn_0803_ModuleControlPart_002());
	} else {
		log("something went wrong");
	}
+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@
 ** @verdict  pass accept, noexecution
 *****************************************************************/

module Syn_0803_ModuleControlPart_001 {
module Syn_15_ModuleControlPart_001 {

type record MyRecord {
	charstring field1
+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@
 ** @verdict  pass accept, noexecution
 *****************************************************************/

module Syn_0803_ModuleControlPart_001 {
module Syn_15_ModuleControlPart_001 {

type record MyRecord {
	default def