Loading 20_statement_and_operations_for_alt/2002_the_alt_statement/Sem_2002_TheAltStatement_010.ttcn +17 −2 Original line number Diff line number Diff line Loading @@ -5,8 +5,23 @@ ** @verdict pass accept, ttcn3verdict:pass *****************************************************************/ //TO_IMPLEMENT module Sem_2002_TheAltStatement_010 { type component GeneralComp { } testcase TC_Sem_2002_TheAltStatement_010() runs on GeneralComp { timer t_timer; t_timer.start(20E-3); alt { // block until a timeout happens in 20ms [] t_timer.timeout { setverdict(pass); } } } control { execute(TC_Sem_2002_TheAltStatement_010(), 200E-3); // timeout in 100ms, then error } } No newline at end of file 20_statement_and_operations_for_alt/2002_the_alt_statement/Sem_2002_TheAltStatement_011.ttcn +23 −2 Original line number Diff line number Diff line Loading @@ -5,8 +5,29 @@ ** @verdict pass accept, ttcn3verdict:pass *****************************************************************/ //TO_IMPLEMENT module Sem_2002_TheAltStatement_011 { type component GeneralComp { } testcase TC_Sem_2002_TheAltStatement_010() runs on GeneralComp { timer t_timer; t_timer.start(20E-3); var boolean v_altVisited := false; alt { // block until a timeout happens in 20ms [] t_timer.timeout { v_altVisited := true; } } if (v_altVisited == true) { setverdict(pass); } else { setverdict(fail); // for some reason the alt has not been processed correctly. } } control { execute(TC_Sem_2002_TheAltStatement_010(), 200E-3); // timeout in 100ms, then error } } No newline at end of file Loading
20_statement_and_operations_for_alt/2002_the_alt_statement/Sem_2002_TheAltStatement_010.ttcn +17 −2 Original line number Diff line number Diff line Loading @@ -5,8 +5,23 @@ ** @verdict pass accept, ttcn3verdict:pass *****************************************************************/ //TO_IMPLEMENT module Sem_2002_TheAltStatement_010 { type component GeneralComp { } testcase TC_Sem_2002_TheAltStatement_010() runs on GeneralComp { timer t_timer; t_timer.start(20E-3); alt { // block until a timeout happens in 20ms [] t_timer.timeout { setverdict(pass); } } } control { execute(TC_Sem_2002_TheAltStatement_010(), 200E-3); // timeout in 100ms, then error } } No newline at end of file
20_statement_and_operations_for_alt/2002_the_alt_statement/Sem_2002_TheAltStatement_011.ttcn +23 −2 Original line number Diff line number Diff line Loading @@ -5,8 +5,29 @@ ** @verdict pass accept, ttcn3verdict:pass *****************************************************************/ //TO_IMPLEMENT module Sem_2002_TheAltStatement_011 { type component GeneralComp { } testcase TC_Sem_2002_TheAltStatement_010() runs on GeneralComp { timer t_timer; t_timer.start(20E-3); var boolean v_altVisited := false; alt { // block until a timeout happens in 20ms [] t_timer.timeout { v_altVisited := true; } } if (v_altVisited == true) { setverdict(pass); } else { setverdict(fail); // for some reason the alt has not been processed correctly. } } control { execute(TC_Sem_2002_TheAltStatement_010(), 200E-3); // timeout in 100ms, then error } } No newline at end of file