Commit 4957854a authored by schmitting's avatar schmitting
Browse files

Work on ISUP part

parent 53dfe324
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+1 −2
Original line number Diff line number Diff line
@@ -111,7 +111,6 @@
						//2: release requested; 3: setup
					var integer v_ISUP_BearerState1; //state associated with cic1
					var integer v_ISUP_BearerState2; //state associated with cic2
					var boolean v_ISUP_inTestBody;
					var boolean v_ACM_expected1; // First IAM sent, ACM pending, if true
					var boolean v_ACM_expected2; // Second IAM sent, ACM pending, if true

+1 −19
Original line number Diff line number Diff line
/*
 *	@author 	STF 297
 *	@author 	STF 366
 *	@version	$Id$
 *	@desc		This module provides test steps (including altsteps) used at the ISUP/BICC side.
*/
@@ -248,7 +248,6 @@ group SipIsup_ISUP_Defaults
			}
	};// end default a_IsupBicc_Def_Generic


}; // end group SipIsup_ISUP_Defaults

group SipIsup_ISUP_Receive_Msgs
@@ -1469,7 +1468,6 @@ group SipIsup_ISUP_Preambles

		v_ISUP_BearerState1 := 0;//initialize bearer state associated with cic1
		v_ISUP_BearerState2 := 0;//initialize bearer state associated with cic2
		v_ISUP_inTestBody := false;

		// Initialize cic values for transmission side
		v_CircuitIdentityCode1 := PX_ISUP_TX_CIC_cicv1;
@@ -1479,22 +1477,6 @@ group SipIsup_ISUP_Preambles
		v_SLS := PX_ISUP_SLS;
		v_SLS2 := int2bit((bit2int(PX_ISUP_SLS) + 1), 4);

/*		if (PX_ISUP_Isup == true)
		{
			IsupBiccP.send (m_InitializeIsup_req);
		}
		else
		{
			IsupBiccP.send (m_InitializeBicc_req);
		}

		TAck.start;

		alt
		{
		  [] IsupBiccP.receive(mw_InitializeIsupBicc_cnf){TAck.stop};
		} 
*/
	} //end function f_IsupBiccPre0

} // end group SipIsup_ISUP_Preambles
+1136 −1133

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