Commit a8130ae1 authored by pintar's avatar pintar
Browse files

new ports are declared UE1, UE2, UE3, PCSCF, SCSCF

parent cfdf7ed6
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+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@
	** @desc  The test system interface
	*/
	type component TestAdapter {
		port SipPort UE1, MW_I1, IC1, ISC1 ;
		port SipPort UE1, UE2, UE3, AS1, PCSCF, SCSCF ;
	}