ARMv4 assembly pack: add Cortex-A15 performance data.

# below and combine it with reduction algorithm from x86 module.

# Performance improvement over previous version varies from 65% on

# Snapdragon S4 to 110% on Cortex A9. In absolute terms Cortex A8

# processes one byte in 8.45 cycles, A9 - in 10.2, Snapdragon S4 -

# in 9.33.

# processes one byte in 8.45 cycles, A9 - in 10.2, A15 - in 7.63,

# Snapdragon S4 - in 9.33.

#

# Cmara, D.; Gouva, C. P. L.; Lpez, J. & Dahab, R.: Fast Software

# Polynomial Multiplication on ARM Processors using the NEON Engine.

# is ~2.5x larger and there are some redundant instructions executed

# when processing last block, improvement is not as big for smallest

# blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per

# byte, which is also >80% faster than integer-only code.

# byte, which is also >80% faster than integer-only code. Cortex-A15

# is even faster spending 5.6 cycles per byte outperforming integer-

# only code by factor of 2.

# May 2014.

#

# terms it's 22.6 cycles per byte, which is disappointing result.

# Technical writers asserted that 3-way S4 pipeline can sustain

# multiple NEON instructions per cycle, but dual NEON issue could

# not be observed, and for NEON-only sequences IPC(*) was found to

# be limited by 1:-( 0.33 and 0.66 were measured for sequences with

# ILPs(*) of 1 and 2 respectively. This in turn means that you can

# even find yourself striving, as I did here, for achieving IPC

# adequate to one delivered by Cortex A8 [for reference, it's

# 0.5 for ILP of 1, and 1 for higher ILPs].

#

# (*) ILP, instruction-level parallelism, how many instructions

#     *can* execute at the same time. IPC, instructions per cycle,

#     indicates how many instructions actually execute.

# not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html

# for further details. On side note Cortex-A15 processes one byte in

# 16 cycles.

# Byte order [in]dependence. =========================================

#