Loading crypto/perlasm/x86unix.pl +3 −3 Original line number Diff line number Diff line Loading @@ -227,9 +227,9 @@ sub main'pxor { &out2("pxor",@_); } sub main'por { &out2("por",@_); } sub main'pand { &out2("pand",@_); } sub main'movq { local($p1,$p2)=@_; if ($p1=~/^mm[0-7]$/ && $p2=~/^mm[0-7]$/) # movq between mmx registers sinks Intel CPUs local($p1,$p2,$optimize)=@_; if ($optimize && $p1=~/^mm[0-7]$/ && $p2=~/^mm[0-7]$/) # movq between mmx registers can sink Intel CPUs { push(@out,"\tpshufw\t\$0xe4,%$p2,%$p1\n"); } else { &out2("movq",@_); } } Loading crypto/sha/asm/sha512-sse2.pl +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ # # 2.4GHz P4 1.4GHz AMD32 1.4GHz AMD64(*) # SHA256/gcc(*) 54 43 59 # SHA512/gcc 17 23 92 # SHA512/gcc 21 24 92 # SHA512/sse2 61(**) 57(**) # SHA512/icc 26 28 # SHA256/icc(*) 65 54 Loading Loading
crypto/perlasm/x86unix.pl +3 −3 Original line number Diff line number Diff line Loading @@ -227,9 +227,9 @@ sub main'pxor { &out2("pxor",@_); } sub main'por { &out2("por",@_); } sub main'pand { &out2("pand",@_); } sub main'movq { local($p1,$p2)=@_; if ($p1=~/^mm[0-7]$/ && $p2=~/^mm[0-7]$/) # movq between mmx registers sinks Intel CPUs local($p1,$p2,$optimize)=@_; if ($optimize && $p1=~/^mm[0-7]$/ && $p2=~/^mm[0-7]$/) # movq between mmx registers can sink Intel CPUs { push(@out,"\tpshufw\t\$0xe4,%$p2,%$p1\n"); } else { &out2("movq",@_); } } Loading
crypto/sha/asm/sha512-sse2.pl +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ # # 2.4GHz P4 1.4GHz AMD32 1.4GHz AMD64(*) # SHA256/gcc(*) 54 43 59 # SHA512/gcc 17 23 92 # SHA512/gcc 21 24 92 # SHA512/sse2 61(**) 57(**) # SHA512/icc 26 28 # SHA256/icc(*) 65 54 Loading