Loading doc/crypto/OPENSSL_ia32cap.pod +7 −6 Original line number Original line Diff line number Diff line Loading @@ -17,18 +17,19 @@ register after executing CPUID instruction with EAX=1 input value (see Intel Application Note #241618). Naturally it's meaningful on IA-32[E] Intel Application Note #241618). Naturally it's meaningful on IA-32[E] platforms only. The variable is normally set up automatically upon platforms only. The variable is normally set up automatically upon toolkit initialization, but can be manipulated afterwards to modify toolkit initialization, but can be manipulated afterwards to modify crypto library behaviour. For the moment of this writing three bits are crypto library behaviour. For the moment of this writing five bits are significant, namely bit #28 denoting Hyperthreading, which is used to significant, namely bit #28 denoting Hyperthreading, which is used to distinguish Intel P4 core, bit #26 denoting SSE2 support, and bit #4 distinguish Intel P4 core, bit #26 denoting SSE2 support, bit #25 denoting presence of Time-Stamp Counter. Clearing bit #26 at run-time denoting SSE support, bit #23 denoting MMX support, and bit #4 denoting for example disables high-performance SSE2 code present in the crypto presence of Time-Stamp Counter. Clearing bit #26 at run-time for example disables high-performance SSE2 code present in the crypto library. You might have to do this if target OpenSSL application is library. You might have to do this if target OpenSSL application is executed on SSE2 capable CPU, but under control of OS which does not executed on SSE2 capable CPU, but under control of OS which does not support SSE2 extentions. Even though you can manipulate the value support SSE2 extentions. Even though you can manipulate the value programmatically, you most likely will find it more appropriate to set programmatically, you most likely will find it more appropriate to set up an environment variable with the same name prior starting target up an environment variable with the same name prior starting target application, e.g. 'env OPENSSL_ia32cap=0x10 apps/openssl', to achieve application, e.g. 'env OPENSSL_ia32cap=0x12800010 apps/openssl', to same effect without modifying the application source code. achieve same effect without modifying the application source code. Alternatively you can reconfigure the toolkit with no-sse2 option and Alternatively you can reconfigure the toolkit with no-sse2 option and recompile. recompile. Loading Loading
doc/crypto/OPENSSL_ia32cap.pod +7 −6 Original line number Original line Diff line number Diff line Loading @@ -17,18 +17,19 @@ register after executing CPUID instruction with EAX=1 input value (see Intel Application Note #241618). Naturally it's meaningful on IA-32[E] Intel Application Note #241618). Naturally it's meaningful on IA-32[E] platforms only. The variable is normally set up automatically upon platforms only. The variable is normally set up automatically upon toolkit initialization, but can be manipulated afterwards to modify toolkit initialization, but can be manipulated afterwards to modify crypto library behaviour. For the moment of this writing three bits are crypto library behaviour. For the moment of this writing five bits are significant, namely bit #28 denoting Hyperthreading, which is used to significant, namely bit #28 denoting Hyperthreading, which is used to distinguish Intel P4 core, bit #26 denoting SSE2 support, and bit #4 distinguish Intel P4 core, bit #26 denoting SSE2 support, bit #25 denoting presence of Time-Stamp Counter. Clearing bit #26 at run-time denoting SSE support, bit #23 denoting MMX support, and bit #4 denoting for example disables high-performance SSE2 code present in the crypto presence of Time-Stamp Counter. Clearing bit #26 at run-time for example disables high-performance SSE2 code present in the crypto library. You might have to do this if target OpenSSL application is library. You might have to do this if target OpenSSL application is executed on SSE2 capable CPU, but under control of OS which does not executed on SSE2 capable CPU, but under control of OS which does not support SSE2 extentions. Even though you can manipulate the value support SSE2 extentions. Even though you can manipulate the value programmatically, you most likely will find it more appropriate to set programmatically, you most likely will find it more appropriate to set up an environment variable with the same name prior starting target up an environment variable with the same name prior starting target application, e.g. 'env OPENSSL_ia32cap=0x10 apps/openssl', to achieve application, e.g. 'env OPENSSL_ia32cap=0x12800010 apps/openssl', to same effect without modifying the application source code. achieve same effect without modifying the application source code. Alternatively you can reconfigure the toolkit with no-sse2 option and Alternatively you can reconfigure the toolkit with no-sse2 option and recompile. recompile. Loading
