Commit 4400f6c6 authored by Andy Polyakov's avatar Andy Polyakov
Browse files

sparcv9cap.c: add Fujitsu SPARC64 X AES capability detection. 



Reviewed-by: default avatarRichard Levitte <levitte@openssl.org>
parent fb65020b

crypto/sparc_arch.h

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
# define SPARCV9_VIS3            (1<<6)

# define SPARCV9_RANDOM          (1<<7)

# define SPARCV9_64BIT_STACK     (1<<8)

# define SPARCV9_FJAESX          (1<<9)/* Fujitsu SPARC64 X AES */



/*

 * OPENSSL_sparcv9cap_P[1] is copy of Compatibility Feature Register,

crypto/sparccpuid.S

+8 −0
Original line number Diff line number Diff line
@@ -349,6 +349,14 @@ _sparcv9_random: 
.type	_sparcv9_random,#function

.size	_sparcv9_random,.-_sparcv9_vis3_probe



.global	_sparcv9_fjaesx_probe

.align	8

_sparcv9_fjaesx_probe:

	.word	0x81b09206	!faesencx %f2,%f6,%f0

	retl

	nop

.size	_sparcv9_fjaesx_probe,.-_sparcv9_fjaesx_probe



.global	OPENSSL_cleanse

.align	32

OPENSSL_cleanse:

crypto/sparcv9cap.c

+11 −5
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ void OPENSSL_cpuid_setup(void) 
            if (vec[0]&0x0080)  OPENSSL_sparcv9cap_P[0] |= SPARCV9_BLK;

            if (vec[0]&0x0100)  OPENSSL_sparcv9cap_P[0] |= SPARCV9_FMADD;

            if (vec[0]&0x0400)  OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3;

            if (vec[0]&0x10000) OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJAESX;



            /* reconstruct %cfr copy */

            OPENSSL_sparcv9cap_P[1] = (vec[0]>>17)&0x3ff;
@@ -233,6 +234,11 @@ void OPENSSL_cpuid_setup(void) 
        OPENSSL_sparcv9cap_P[0] |= SPARCV9_VIS3;

    }



    if (sigsetjmp(common_jmp, 1) == 0) {

        _sparcv9_fjaesx_probe();

        OPENSSL_sparcv9cap_P[0] |= SPARCV9_FJAESX;

    }



    /*

     * In wait for better solution _sparcv9_rdcfr is masked by

     * VIS3 flag, because it goes to uninterruptable endless