Loading crypto/poly1305/asm/poly1305-sparcv9.pl +2 −2 Original line number Diff line number Diff line Loading @@ -74,8 +74,8 @@ poly1305_init: SPARC_LOAD_ADDRESS(OPENSSL_sparcv9cap_P,%g1) ld [%g1],%g1 and %g1,SPARCV9_FMADD|SPARCV9_PREFER_FPU|SPARCV9_VIS3,%g1 cmp %g1,SPARCV9_FMADD|SPARCV9_PREFER_FPU and %g1,SPARCV9_FMADD|SPARCV9_VIS3,%g1 cmp %g1,SPARCV9_FMADD be .Lpoly1305_init_fma nop Loading crypto/sparcv9cap.c +12 −3 Original line number Diff line number Diff line Loading @@ -60,9 +60,18 @@ int bn_mul_mont(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp, if ((OPENSSL_sparcv9cap_P[0] & SPARCV9_VIS3)) return bn_mul_mont_vis3(rp, ap, bp, np, n0, num); else if (num >= 8 && /* * bn_mul_mont_fpu doesn't use FMADD, we just use the * flag to detect when FPU path is preferable in cases * when current heuristics is unreliable. [it works * out because FMADD-capable processors where FPU * code path is undesirable are also VIS3-capable and * VIS3 code path takes precedence.] */ ( (OPENSSL_sparcv9cap_P[0] & SPARCV9_FMADD) || (OPENSSL_sparcv9cap_P[0] & (SPARCV9_PREFER_FPU | SPARCV9_VIS1)) == (SPARCV9_PREFER_FPU | SPARCV9_VIS1)) (SPARCV9_PREFER_FPU | SPARCV9_VIS1) )) return bn_mul_mont_fpu(rp, ap, bp, np, n0, num); } return bn_mul_mont_int(rp, ap, bp, np, n0, num); Loading Loading
crypto/poly1305/asm/poly1305-sparcv9.pl +2 −2 Original line number Diff line number Diff line Loading @@ -74,8 +74,8 @@ poly1305_init: SPARC_LOAD_ADDRESS(OPENSSL_sparcv9cap_P,%g1) ld [%g1],%g1 and %g1,SPARCV9_FMADD|SPARCV9_PREFER_FPU|SPARCV9_VIS3,%g1 cmp %g1,SPARCV9_FMADD|SPARCV9_PREFER_FPU and %g1,SPARCV9_FMADD|SPARCV9_VIS3,%g1 cmp %g1,SPARCV9_FMADD be .Lpoly1305_init_fma nop Loading
crypto/sparcv9cap.c +12 −3 Original line number Diff line number Diff line Loading @@ -60,9 +60,18 @@ int bn_mul_mont(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp, if ((OPENSSL_sparcv9cap_P[0] & SPARCV9_VIS3)) return bn_mul_mont_vis3(rp, ap, bp, np, n0, num); else if (num >= 8 && /* * bn_mul_mont_fpu doesn't use FMADD, we just use the * flag to detect when FPU path is preferable in cases * when current heuristics is unreliable. [it works * out because FMADD-capable processors where FPU * code path is undesirable are also VIS3-capable and * VIS3 code path takes precedence.] */ ( (OPENSSL_sparcv9cap_P[0] & SPARCV9_FMADD) || (OPENSSL_sparcv9cap_P[0] & (SPARCV9_PREFER_FPU | SPARCV9_VIS1)) == (SPARCV9_PREFER_FPU | SPARCV9_VIS1)) (SPARCV9_PREFER_FPU | SPARCV9_VIS1) )) return bn_mul_mont_fpu(rp, ap, bp, np, n0, num); } return bn_mul_mont_int(rp, ap, bp, np, n0, num); Loading