module LibItsRtcmem_TestSystem {
    
    // LibCommon
    import from LibCommon_BasicTypesAndValues all;
    import from LibCommon_Time all;
    import from LibCommon_Sync all;
    import from LibCommon_DataStrings all;

    // LibIts
    import from ITS_Container language "ASN.1:1997" all;
    import from RTCMEM_PDU_Descriptions language "ASN.1:1997" all;
    import from EfcDsrcGeneric language "ASN.1:1997" all;

    // LibItsCommon
    import from LibItsCommon_TestSystem all;
    import from LibItsCommon_TypesAndValues all;
    
    // LibItsRtcmem
    import from LibItsRtcmem_TypesAndValues all;
    
    group portDefinitions {
        
        /**
         * @desc Adapter control port
         */
        type port AdapterControlPort message {
            out
                AcSecPrimitive;
            in
                AdapterControlResults;
        } // end AdapterControlPort
        
        /**
         * @desc Upper Tester port
         */
        type port UpperTesterPort message {
            out 
                UtRtcmemInitialize, UtRtcmemTrigger, UtRtcmemUpdate, UtRtcmemTermination;
            in 
                UtRtcmemResults, UtRtcmemEventInd;
        } // end UpperTesterPort

    } // end portDefinitions

    group interfacePorts {

        /**
        * @desc Application MapSpat Port
        */
        type port RtcmemPort message {
             in RtcmemInd;
             out RtcmemReq
        }
    
    } // End of group interfacePorts

    /**
    * @desc ITS System Adapter
    */
    type component ItsRtcmemSystem {
            
        port AdapterControlPort acPort;
        port UpperTesterPort utPort;
        port RtcmemPort rtcmemPort;

    } // End of component ITS System Adapter
     
    /**
     * @desc Test component for ITS SREM-SSEM application layer 
     */
    type component ItsRtcmem extends ItsBaseComponent {

        port AdapterControlPort acPort;
        port UpperTesterPort utPort;
        port RtcmemPort rtcmemPort;
        //timers
        
        //component variables
        var RtcmemInd vc_mapMsg;
        var UtRtcmemEventIndList vc_utEvents := {};
        
        //default
        var default vc_default := null;
        
        //global variables
        var boolean vc_rtcmemReceived := false;
        
        var boolean vc_rtcmemDefaultActive := true;
    } // End of component ItsRtcmem

    group ApplPrimitives {
        
        type record RtcmemInd {
            RTCMEM      msgIn,
            UInt64      recvTime optional,
            UInt8       gnNextHeader optional,
            UInt8       gnHeaderType optional,
            UInt8       gnHeaderSubtype optional,
            UInt32      gnLifetime optional,
            UInt8       gnTrafficClass optional,
            UInt16      btpDestinationPort optional,
            UInt16      btpInfo optional,
            Bit24       ssp optional,
            UInt32      its_aid optional
        }
        with {
            encode (msgIn) "PER"
        }
        
        type record of RtcmemInd RtcmemInds;
        
        /**
        * @desc Appl SREM and SSEM Request Primitive 
        */
        type record RtcmemReq { 
            RTCMEM msgOut 
        }
        with {
            encode (msgOut) "PER"
        }
            
    } with {
        variant ""
        encode "LibIts_Interface" 
    } // End of group ApplPrimitives
    
} // End of module LibItsRtcmem_TestSystem