/** * @author ETSI STF517 / STF581 / TTF002 * @version $Url: https://oldforge.etsi.org/svn/LibIts/tags/20170222_STF527_Final/ttcn/SremSsem/LibItsSremSsem_TestSystem.ttcn $ * $Id: LibItsSremSsem_TestSystem.ttcn,v 1.2 2018/05/31 15:57:11 dte Exp $ * @desc Test System module for ITS SREM SSEM * @copyright ETSI Copyright Notification * No part may be reproduced except as authorized by written permission. * The copyright and the foregoing restriction extend to reproduction in all media. * All rights reserved. * */ module LibItsSremSsem_TestSystem { // LibCommon import from LibCommon_BasicTypesAndValues all; import from LibCommon_Time all; import from LibCommon_Sync all; import from LibCommon_DataStrings all; // LibIts import from ITS_Container language "ASN.1:1997" all; import from SREM_PDU_Descriptions language "ASN.1:1997" all; import from SSEM_PDU_Descriptions language "ASN.1:1997" all; import from EfcDsrcGeneric language "ASN.1:1997" all; // LibItsCommon import from LibItsCommon_TestSystem all; import from LibItsCommon_TypesAndValues all; // LibItsSremSsem import from LibItsSremSsem_TypesAndValues all; group portDefinitions { /** * @desc Adapter control port */ type port AdapterControlPort message { out AcSecPrimitive; in AdapterControlResults; } // end AdapterControlPort /** * @desc Upper Tester port */ type port UpperTesterPort message { out UtSremInitialize, UtSremTrigger, UtSremUpdate, UtSremCancelation; in UtSremResults, UtSremEventInd , UtSsemEventInd; } // end UpperTesterPort } // end portDefinitions group interfacePorts { /** * @desc Application MapSpat Port */ type port SremSsemPort message { in SremInd , SsemInd ; out SremReq , SsemReq } } // End of group interfacePorts /** * @desc ITS System Adapter */ type component ItsSremSsemSystem { port AdapterControlPort acPort; port UpperTesterPort utPort; port SremSsemPort sremSsemPort; } // End of component ITS System Adapter /** * @desc Test component for ITS SREM-SSEM application layer */ type component ItsSremSsem extends ItsBaseComponent { port AdapterControlPort acPort; port UpperTesterPort utPort; port SremSsemPort sremSsemPort; //timers //component variables var SremInd vc_mapMsg; var SsemInd vc_spatMsg; var UtSremEventIndList vc_utSremEvents := {}; var UtSsemEventIndList vc_utSsemEvents := {}; //default var default vc_default := null; //global variables var boolean vc_sremReceived := false; var boolean vc_ssemReceived := false; var boolean vc_sremSsemDefaultActive := true; } // End of component ItsSremSsem group ApplPrimitives { type record SremInd { SREM msgIn, UInt64 recvTime optional, UInt8 gnNextHeader optional, UInt8 gnHeaderType optional, UInt8 gnHeaderSubtype optional, UInt32 gnLifetime optional, UInt8 gnTrafficClass optional, UInt16 btpDestinationPort optional, UInt16 btpInfo optional, Bit24 ssp optional, UInt32 its_aid optional } with { encode (msgIn) "PER" } type record of SremInd SremInds; type record SsemInd { SSEM msgIn, UInt64 recvTime optional, UInt8 gnNextHeader optional, UInt8 gnHeaderType optional, UInt8 gnHeaderSubtype optional, UInt32 gnLifetime optional, UInt8 gnTrafficClass optional, UInt16 btpDestinationPort optional, UInt16 btpInfo optional, Bit24 ssp optional, UInt32 its_aid optional } with { encode (msgIn) "PER" } /** * @desc Appl SREM and SSEM Request Primitive */ type record SremReq { SREM msgOut } with { encode (msgOut) "PER" } type record SsemReq { SSEM msgOut } with { encode (msgOut) "PER" } } with { variant "" encode "LibIts_Interface" } // End of group ApplPrimitives } // End of module LibItsSremSsem_TestSystem