Loading ttcn/DCC/LibItsDcc_Pixits.ttcn +2 −2 Original line number Diff line number Diff line Loading @@ -760,7 +760,7 @@ module LibItsDcc_Pixits { * @desc Give the content of Table 34 * @see ETSI TS 102 917-2 Table 34 */ modulepar ChannelProfileAspects PIXIT_TABLE_34_TC_G5B_SCH4_01_02 := { modulepar ChannelProfileAspects PIXIT_TABLE_34_TC_G5B_SCH4_01_03 := { { active, { 9, 10, 11, 12, 13, 14, 15, 16, 20, 21, 22, 23, 24 } }, Loading @@ -773,7 +773,7 @@ module LibItsDcc_Pixits { * @desc Give the content of Table 34 only SCH3 state * @see ETSI TS 102 917-2 Table 34 */ modulepar ChannelStates PIXIT_TABLE_34_TC_G5B_SCH4_03_SCH3 := { modulepar ChannelStates PIXIT_TABLE_34_TC_G5B_SCH4_01_03_SCH3 := { active, restrictive } Loading Loading
ttcn/DCC/LibItsDcc_Pixits.ttcn +2 −2 Original line number Diff line number Diff line Loading @@ -760,7 +760,7 @@ module LibItsDcc_Pixits { * @desc Give the content of Table 34 * @see ETSI TS 102 917-2 Table 34 */ modulepar ChannelProfileAspects PIXIT_TABLE_34_TC_G5B_SCH4_01_02 := { modulepar ChannelProfileAspects PIXIT_TABLE_34_TC_G5B_SCH4_01_03 := { { active, { 9, 10, 11, 12, 13, 14, 15, 16, 20, 21, 22, 23, 24 } }, Loading @@ -773,7 +773,7 @@ module LibItsDcc_Pixits { * @desc Give the content of Table 34 only SCH3 state * @see ETSI TS 102 917-2 Table 34 */ modulepar ChannelStates PIXIT_TABLE_34_TC_G5B_SCH4_03_SCH3 := { modulepar ChannelStates PIXIT_TABLE_34_TC_G5B_SCH4_01_03_SCH3 := { active, restrictive } Loading