Commit 23ccd677 authored by berge's avatar berge
Browse files

Added LibIts_SystemAdapter module to resolve cyclic import

parent 3275edd0
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+5 −4
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@@ -10,6 +10,7 @@ module LibIts_Interface {
    // LibIts
    import from LibItsCam_Pixits all;
    import from LibItsGeoNetworking_TypesAndValues all;
    import from LibIts_SystemAdapter all;
    
    // LibCommon
    import from LibCommon_Time {modulepar all};
@@ -19,7 +20,7 @@ module LibIts_Interface {
        /**
         * @desc Test component for ITS Access layer 
         */
        type component ItsAc {
        type component ItsAc extends ItsAdapterComponent {
            
            // AC1 ports
            port MacM5Port macM5Port;
@@ -31,7 +32,7 @@ module LibIts_Interface {
        /**
         * @desc Test component for ITS Facility layer 
         */
        type component ItsFa {
        type component ItsFa extends ItsAdapterComponent {
            
            // FA1 ports
            port CamPort camPort;
@@ -50,7 +51,7 @@ module LibIts_Interface {
        /**
         * @desc Test component for ITS Management layer 
         */
        type component ItsMgt {
        type component ItsMgt extends ItsAdapterComponent {
            
            // MGT1 ports
            port IiscPort iiscPort;
@@ -59,7 +60,7 @@ module LibIts_Interface {
        /**
         * @desc Test component for ITS Network and Transport layer 
         */
        type component ItsNt {
        type component ItsNt extends ItsAdapterComponent {
            
            // NT1 ports 
            port BtpPort btpPort;
+40 −0
Original line number Diff line number Diff line
/**
 *	@author 	ETSI / STF405
 *  @version 	$URL$
 *				$Id$
 *	@desc		System Adapter specific port and component definition
 *
 */
module LibIts_SystemAdapter {
    
    group portDefinitions {
    
    	/**
    	 * @desc Adapter control port
    	 */
    	type port AdapterControlPort message {
    	    in integer; //TODO: remove me
    	} // end AdapterControlPort

    	/**
    	 * @desc Upper Tester port
    	 */
    	type port UpperTesterPort message {
    	    in integer; //TODO: remove me
    	} // end UpperTesterPort
    	
    } // end portDefinitions
    
    group adapterComponent {
        
        type component ItsAdapterComponent {
            
     	    // Adapter ports
    	    port UpperTesterPort utPort;
            port AdapterControlPort acPort;
            
        } // end AdapterComponent
           
    } // end adapterComponent
    
} // end LibIts_SystemAdapter
 No newline at end of file
+1 −18
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@@ -8,29 +8,12 @@
module LibIts_TestSystem {
    
    // LibITS
    import from LibIts_SystemAdapter all;
    import from LibIts_Interface all;
    
    // LibCommon
    import from LibCommon_Time {modulepar all};
    
    group portDefinitions {
    
    	/**
    	 * @desc Adapter control port
    	 */
    	type port AdapterControlPort message {
    	    in integer; //TODO: remove me
    	} // end AdapterControlPort

    	/**
    	 * @desc Upper Tester port
    	 */
    	type port UpperTesterPort message {
    	    in integer; //TODO: remove me
    	} // end UpperTesterPort
    	
    } // end portDefinitions

	group componentDefinitions {

    	/**