Commit 7ea95047 authored by garciay's avatar garciay
Browse files

RSUsimulator: Add PICS_GENERATE_xxx

parent 2e1a0f62
...@@ -70,7 +70,7 @@ module ItsRSUsSimulator_Functions { ...@@ -70,7 +70,7 @@ module ItsRSUsSimulator_Functions {
f_initialiseSecuredMode(); f_initialiseSecuredMode();
//Initialze the IUT //Initialze the IUT
f_initialState(); // f_initialState();
// Initialisations // Initialisations
vc_longPosVectorRsu := PICS_RSU_PARAMS[PX_RSU_ID - 1].longPosVector; vc_longPosVectorRsu := PICS_RSU_PARAMS[PX_RSU_ID - 1].longPosVector;
......
...@@ -41,7 +41,7 @@ module ItsRSUsSimulator_TestCases { ...@@ -41,7 +41,7 @@ module ItsRSUsSimulator_TestCases {
if (isbound(vc_rsuMessagesValueList[PX_RSU_ID - 1].cam)) { if (isbound(vc_rsuMessagesValueList[PX_RSU_ID - 1].cam)) {
tc_cam.start; tc_cam.start;
} }
if (isbound(vc_rsuMessagesValueList[PX_RSU_ID - 1].denm)) { if (isbound(vc_rsuMessagesValueList[PX_RSU_ID - 1].denms)) {
tc_denm.start; tc_denm.start;
} }
if (isbound(vc_rsuMessagesValueList[PX_RSU_ID - 1].mapem)) { if (isbound(vc_rsuMessagesValueList[PX_RSU_ID - 1].mapem)) {
...@@ -70,15 +70,17 @@ module ItsRSUsSimulator_TestCases { ...@@ -70,15 +70,17 @@ module ItsRSUsSimulator_TestCases {
repeat; repeat;
} }
[] tc_cam.timeout { [] tc_cam.timeout {
log("*** " & testcasename() & ": DEBUG: Processing CAM ***");
f_prepare_cam(v_payload); f_prepare_cam(v_payload);
f_send(v_payload); f_send(v_payload);
tc_cam.start; tc_cam.start;
repeat; repeat;
} }
[] tc_denm.timeout { [] tc_denm.timeout {
log("*** " & testcasename() & ": DEBUG: Processing DENM ***");
f_prepare_denm(v_payload); f_prepare_denm(v_payload);
f_send(v_payload); f_send(v_payload);
tc_cam.start; tc_denm.start;
repeat; repeat;
} }
// [] tc_spatem.timeout { // [] tc_spatem.timeout {
......
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