Remove PICS_RSU

ttcn/AtsSremSsem/ItsSrem_TestControl.ttcn

@@ -20,41 +20,32 @@ module ItsSrem_TestControl {
     // Test Execution
     control {
         
-        if (not PICS_RSU_ROLE) {
+        if (PICS_SREM_GENERATION) {
             
-            if (PICS_SREM_GENERATION) {
-                
-                execute(TC_IS_RLT_MSGF_BV_01());
-                execute(TC_IS_TLC_EVGN_BV_01());
-                execute(TC_IS_TLC_EVGN_BV_02());
-                execute(TC_IS_TLC_COMM_BV_01_01());
-                execute(TC_IS_TLC_COMM_BV_01_02());
-                
-                if (PICS_SSEM_RECEPTION) {
-                    
-                    execute(TC_IS_TLC_MSGF_BV_03());
-                    
-                }
-                
-            }
+            execute(TC_IS_RLT_MSGF_BV_01());
+            execute(TC_IS_TLC_EVGN_BV_01());
+            execute(TC_IS_TLC_EVGN_BV_02());
+            execute(TC_IS_TLC_COMM_BV_01_01());
+            execute(TC_IS_TLC_COMM_BV_01_02());
+        }
+        if (PICS_SSEM_RECEPTION) {
+            
+            execute(TC_IS_TLC_MSGF_BV_03());
             
         }
         
-        if (PICS_RSU_ROLE) {
+        if (PICS_SREM_GENERATION) {
             
-            if (PICS_SREM_GENERATION) {
-                
-                execute(TC_IS_TLC_MSGF_BV_04());
-                
-                if (PICS_SREM_RECEPTION) {
-                    
-                    execute(TC_IS_TLC_MSGF_BV_02());
-                    
-                }
-                
-            }
+            execute(TC_IS_TLC_MSGF_BV_04());
             
         }
+        
+        if (PICS_SREM_RECEPTION) {
+            
+            execute(TC_IS_TLC_MSGF_BV_02());
+            
+        }
+        
     }
     
 } // End of module ItsSrem_TestControl 
\ No newline at end of file