Loading ccsrc/EncDec/module.mk +1 −0 Original line number Original line Diff line number Diff line Loading @@ -28,6 +28,7 @@ sources += \ LibItsHttp_Encdec.cc \ LibItsHttp_Encdec.cc \ LibItsMapemSpatem_Encdec.cc \ LibItsMapemSpatem_Encdec.cc \ LibItsSremSsem_Encdec.cc \ LibItsSremSsem_Encdec.cc \ LibItsRtcmem_Encdec.cc \ LibItsIvim_Encdec.cc \ LibItsIvim_Encdec.cc \ LibItsPki_Encdec.cc LibItsPki_Encdec.cc Loading ccsrc/Ports/LibIts_ports/UpperTesterPort.hh +2 −2 Original line number Original line Diff line number Diff line Loading @@ -56,7 +56,7 @@ #include "Rtcmem_ports/UpperTesterPort_Rtcmem.hh" #include "Rtcmem_ports/UpperTesterPort_Rtcmem.hh" #endif #endif #ifdef AtsRSUsSimulator // Thsi is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #ifdef AtsRSUsSimulator // This is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #include "GN_ports/UpperTesterPort_GN.hh" #include "GN_ports/UpperTesterPort_GN.hh" #include "BTP_ports/UpperTesterPort_BTP.hh" #include "BTP_ports/UpperTesterPort_BTP.hh" #include "CAM_ports/UpperTesterPort_CAM.hh" #include "CAM_ports/UpperTesterPort_CAM.hh" Loading Loading @@ -121,7 +121,7 @@ #include "UpperTesterPort_Rtcmem.hh" #include "UpperTesterPort_Rtcmem.hh" #endif #endif #ifdef AtsRSUsSimulator // Thsi is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #ifdef AtsRSUsSimulator // This is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #include "UpperTesterPort_GN.hh" #include "UpperTesterPort_GN.hh" #include "UpperTesterPort_BTP.hh" #include "UpperTesterPort_BTP.hh" #include "UpperTesterPort_CAM.hh" #include "UpperTesterPort_CAM.hh" Loading ttcn/AtsRSUsSimulator/module.mk +5 −0 Original line number Original line Diff line number Diff line Loading @@ -37,6 +37,7 @@ modules := ../LibCommon \ ../../ccsrc/Ports/LibIts_ports/IVIM_ports \ ../../ccsrc/Ports/LibIts_ports/IVIM_ports \ ../../ccsrc/Ports/LibIts_ports/MapemSpatem_ports \ ../../ccsrc/Ports/LibIts_ports/MapemSpatem_ports \ ../../ccsrc/Ports/LibIts_ports/SremSsem_ports \ ../../ccsrc/Ports/LibIts_ports/SremSsem_ports \ ../../ccsrc/Ports/LibIts_ports/Rtcmem_ports \ ../../ccsrc/Ports/LibIts_ports/Pki_ports \ ../../ccsrc/Ports/LibIts_ports/Pki_ports \ ../../ccsrc/Ports/LibIts_ports/RSUsSimulator_ports \ ../../ccsrc/Ports/LibIts_ports/RSUsSimulator_ports \ ../../ccsrc/EncDec \ ../../ccsrc/EncDec \ Loading @@ -55,5 +56,9 @@ modules := ../LibCommon \ ../../ccsrc/Protocols/DENM \ ../../ccsrc/Protocols/DENM \ ../../ccsrc/Protocols/IVIM \ ../../ccsrc/Protocols/IVIM \ ../../ccsrc/Protocols/MapemSpatem \ ../../ccsrc/Protocols/MapemSpatem \ ../../ccsrc/Protocols/Rtcmem \ ../../ccsrc/Protocols/SremSsem \ ../../ccsrc/Protocols/SremSsem \ Loading
ccsrc/EncDec/module.mk +1 −0 Original line number Original line Diff line number Diff line Loading @@ -28,6 +28,7 @@ sources += \ LibItsHttp_Encdec.cc \ LibItsHttp_Encdec.cc \ LibItsMapemSpatem_Encdec.cc \ LibItsMapemSpatem_Encdec.cc \ LibItsSremSsem_Encdec.cc \ LibItsSremSsem_Encdec.cc \ LibItsRtcmem_Encdec.cc \ LibItsIvim_Encdec.cc \ LibItsIvim_Encdec.cc \ LibItsPki_Encdec.cc LibItsPki_Encdec.cc Loading
ccsrc/Ports/LibIts_ports/UpperTesterPort.hh +2 −2 Original line number Original line Diff line number Diff line Loading @@ -56,7 +56,7 @@ #include "Rtcmem_ports/UpperTesterPort_Rtcmem.hh" #include "Rtcmem_ports/UpperTesterPort_Rtcmem.hh" #endif #endif #ifdef AtsRSUsSimulator // Thsi is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #ifdef AtsRSUsSimulator // This is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #include "GN_ports/UpperTesterPort_GN.hh" #include "GN_ports/UpperTesterPort_GN.hh" #include "BTP_ports/UpperTesterPort_BTP.hh" #include "BTP_ports/UpperTesterPort_BTP.hh" #include "CAM_ports/UpperTesterPort_CAM.hh" #include "CAM_ports/UpperTesterPort_CAM.hh" Loading Loading @@ -121,7 +121,7 @@ #include "UpperTesterPort_Rtcmem.hh" #include "UpperTesterPort_Rtcmem.hh" #endif #endif #ifdef AtsRSUsSimulator // Thsi is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #ifdef AtsRSUsSimulator // This is not an Abstract Test Suit, but an helper tool to simulate basic RSU/OBU functionalities #include "UpperTesterPort_GN.hh" #include "UpperTesterPort_GN.hh" #include "UpperTesterPort_BTP.hh" #include "UpperTesterPort_BTP.hh" #include "UpperTesterPort_CAM.hh" #include "UpperTesterPort_CAM.hh" Loading
ttcn/AtsRSUsSimulator/module.mk +5 −0 Original line number Original line Diff line number Diff line Loading @@ -37,6 +37,7 @@ modules := ../LibCommon \ ../../ccsrc/Ports/LibIts_ports/IVIM_ports \ ../../ccsrc/Ports/LibIts_ports/IVIM_ports \ ../../ccsrc/Ports/LibIts_ports/MapemSpatem_ports \ ../../ccsrc/Ports/LibIts_ports/MapemSpatem_ports \ ../../ccsrc/Ports/LibIts_ports/SremSsem_ports \ ../../ccsrc/Ports/LibIts_ports/SremSsem_ports \ ../../ccsrc/Ports/LibIts_ports/Rtcmem_ports \ ../../ccsrc/Ports/LibIts_ports/Pki_ports \ ../../ccsrc/Ports/LibIts_ports/Pki_ports \ ../../ccsrc/Ports/LibIts_ports/RSUsSimulator_ports \ ../../ccsrc/Ports/LibIts_ports/RSUsSimulator_ports \ ../../ccsrc/EncDec \ ../../ccsrc/EncDec \ Loading @@ -55,5 +56,9 @@ modules := ../LibCommon \ ../../ccsrc/Protocols/DENM \ ../../ccsrc/Protocols/DENM \ ../../ccsrc/Protocols/IVIM \ ../../ccsrc/Protocols/IVIM \ ../../ccsrc/Protocols/MapemSpatem \ ../../ccsrc/Protocols/MapemSpatem \ ../../ccsrc/Protocols/Rtcmem \ ../../ccsrc/Protocols/SremSsem \ ../../ccsrc/Protocols/SremSsem \