Commit b91f56ce authored by petersenj's avatar petersenj
Browse files

Changed all configuration Up to include validation i.e. f_cfMseUp_val

parent 0ec286f5
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+0 −6
Original line number Diff line number Diff line
@@ -642,11 +642,5 @@ module dPMR_Pics {

	}

	group ValidationGroup {
		/**
		* @desc  	Use validation?
		*/
		modulepar {boolean PIC_VALIDATION := true}
	}

} // end module dPMR_PICS
+6 −0
Original line number Diff line number Diff line
@@ -148,5 +148,11 @@ module dPMR_Pixits {
		modulepar {boolean PXT_DEBUG := true;}
	
	}//end additional
	group ValidationGroup {
		/**
		* @desc  	Use validation?
		*/
		modulepar {boolean PXT_VALIDATION := true}
	}

} // end module dPMR_Pixits 
+689 −166

File changed.

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+24 −12
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ module dPMR_TestConfiguration {
	import from dPMR_Messages all;
//	import from dPMR_Templates all;
	import from dPMR_TestSystem all;
//	import from dPMR_Pixits all;
	import from dPMR_Pixits all;
//	import from dPMR_ExternalFns all;
	

@@ -81,6 +81,7 @@ group configFns {
		out Mse p_ut_val)
	runs on ServerSyncComp {

		if (PXT_VALIDATION) {
			//create
			p_mse := Mse.create("MS Emulation");
			p_ut := Ut.create("Upper Tester");
@@ -93,6 +94,17 @@ group configFns {
			connect(p_mse:dp1Port, p_mse_val:dp1Port);
			connect(p_mse:taPort, p_mse_val:taPort);
			connect(p_ut:utPort, p_ut_val:utPort);
		} else {
			p_mse := Mse.create("MS Emulation");
		  	p_ut := Ut.create("Upper Tester");
			//Connect
			connect(p_mse:syncPort, self:syncPort);
			connect(p_ut:syncPort, self:syncPort);
			//Map
			map(p_mse:dp1Port, system:taDp1Port);
			map(p_mse:taPort, system:taTaPort);
			map(p_ut:utPort, system:taUtPort);
		}

	}//end f_cfMseUp_val